影音先锋在线看片资源蜜桃视频,一及片高清无码视频

For example, the CPP of TSMC's 7nm chips is 57nm, and the MMP is 40nm, similar toSamsung, with the two figures being 54nm and 36nm, respectively, which are both much larger than the 7nm° that semiconductor fabricators claim. The corresponding number of transistors per square millimeter of 10nm node for major chipmakers like Intel, TSMC and Samsung, is 1.06 million, 530,000 and 520,000, respectively. In the past Intel is used to use the channel length (smaller than the gate length) to define the node in order to closely follow Moore's law. Regardless of the reason, the company losed out in the competition.

For example, Intel's 10nm process featured higher transistor density than TSMC's and Samsung's 7nm processes, but from the perspective of marketing, Intel burned its fingers due to the lack of knowledge. Later Intel also followed the rivals, changed to such node naming as intel4, intel3. The above information shows that the node naming is a word game, and the 7nm process corresponds to the MMP in 36nm-40nm.

With this understanding, we can now discuss the relationship between DUV lithography machines with a wavelength of 193nm and the production of 7nm chips. In other words, how does DUV lithography, with its 193nm light source, produce chips with MMP OF 36nm-40nm, as required for 7nm technology? The gap was bridged thanks to the iteration from DUV dry lithography to DUV immersion lithography.

Although the wavelength of DUV lithography machine's light source is only 193nm, light experiences refraction when passing through water, effectively shortening the wavelength. The refractive index of 193nm ultraviolet light in water is approximately 1.44, resulting in a wavelength of around 134nm. Building upon this principle, immersion lithography was proposed by Burn J. LIN in 1987 by introducing a layer of ultra-pure water between the wafer surface and the lens of the lithography machine. The water causes the ultraviolet light to refract, effectively reducing the wavelength to 134nm. In 2003, ASML in the Netherlands successfully developed the first immersion lithography machine based on this concept.

The introduction of immersion lithography machines reduced the gap between 193nm light source and 36nm MMP.

Multiple Exposure

The emergence of immersion lithography has once again reduced the gap with the "7nm", but the industry still cannot directly produce the so-called "7nm" chips. If chip manufacturers truly want to manufacture the 7nm Kirin 9000S, double exposure and multiple exposures are essential.

To explain the double exposure technique, let's use a photography example. Suppose you are a photographer tasked with taking a picture of a lineup of athletes. This lineup consists of only 20 people, spaced 2 meters apart, making it look very sparse. How do you make it appear as if there are 40 people? You have a solution: take the first shot, then have each person shift 1 meter and take another shot. Then, you can merge the two photos together with software.

Double exposure technology works in a similar way. Using one set of mask plates, you create lines with a spacing of 134nm. Then, you shift them a certain distance with another set of masks to create another set of lines with a 134nm spacing. Combining these two, you will have lines with a 67nm spacing, which is a step closer to the desired 36nm. The industry began using double exposure techniques starting from the 22/20nm nodes.

To achieve double exposure, the industry developed the LELE method (Lithography-Etch-Lithography-Etch). It involves applying the photoresist twice and exposing it twice. The first exposure replicates the pattern on a hard mask, while the second exposure replicates the minimum line width pattern on the photoresist. However, a double exposure approach significantly increases manufacturing costs and extends the time required. It's important to note that lithography accounts for about 50% of the entire manufacturing time, and doubling the exposure significantly prolongs the overall manufacturing time.

To address this, the industry developed a more efficient method known as Self-Aligned Double Patterning (SADP), which reduces the two photoresist applications to just one. It utilizes Chemical Vapor Deposition (CVD) technology to deposit silicon oxide around the first photoresist layer, naturally forming the aligned processing positions for the second pattern, allowing for the second exposure.

With these techniques, double exposure can achieve the MMP of 67nm, but it's still two times short of the required 36nm for producing 7nm chips. One way to solve this problem is by using another round of double exposure, for a total of four exposures. This can achieve a minimum line width of 34nm, which is just what's needed for the MMP of 7nm. However, this method comes at a significant cost. Exposure time is four times that of a single exposure, more masks are required, and additional processes such as photoresist coating, soft baking, alignment, development, rinse, hard baking, and pattern inspection are needed for each exposure. The total manufacturing process has increased from a few hundred to thousands of steps, which significantly increases the time and material costs of manufacturing.

Additionally, the increased exposure time can cause lens overheating, which in turn leads to lens aberrations, making overlay accuracy harder to control. Matching film and etching processes also become more challenging. This analysis doesn't consider the impact of Numerical Aperture (NA) on lithography accuracy (this is not detailed here since it doesn't directly relate to understanding multiple exposures). To increase NA, larger lenses are needed.

Using multiple exposure techniques, TSMC started producing 7nm chips (N7) using DUV in June 2016, and Samsung began mass production of 7nm chips (7LPP) in 2018. Only then did using DUV to produce 7nm chips become a reality.

In summary, although it's possible to use DUV with 193nm light sources to manufacture 7nm chips with multiple exposure techniques , the time, material, and labor costs all increase significantly. Due to the substantial increase in process steps, yield can also be impacted.

As a comparison, EUV lithography with its wavelength of 13.5nm allows for the production of 7nm chips in a single exposure. However, EUV faced delays and was only officially adopted in the 5nm process in 2020. Prior to that, GlobalFoundries abandoned 7nm technology development due to its high cost.

DUV and 5-namimeter chip

In addition to multiple exposure techniques, using DUV to manufacture 7nm chips requires the coordination of various technologies, including Phase Shift Masks (PSM), Off-Axis Illumination, Optical Proximity Correction (OPC), Source-Mask Optimization (SMO), and lithography. These technologies gave rise to a new subfield called Computational

Lithography. The enormous data required for computational lithography led NVIDIA's GPUs to become essential tools, with the cuLitho, a software acceleration library, claiming to speed up computational lithography by 40 times.

Computational lithography is necessary because when the lines on the mask plate become very small, UV light passing through the mask creates distortions, affecting the lithographic pattern. Researchers came up with a method to pre-calculate possible distortions on the mask and then design the optimal shape of the mask for lithography to counteract these distortions. This is known as Inverse Lithography Calculation, and it requires massive computational power that regular computers can't handle, leading researchers to use supercomputers and cloud computing.

Meanwhile, researchers applied machine learning algorithms from artificial intelligence to computational lithography. Next-generation Convolutional Neural Networks (CNNs) were used in lithography process modeling, mask optimization, SEM data processing, etc. The training of data required massive GPU clusters. In addition to optimizing the devices, researchers also consider factors in circuit design in device manufacturing, a concept known as Design and Technology Co-Optimization (DTCO), which required EDA vendors to upgrade algorithms and software.

In conclusion, the industry has gone to great lengths to make DUV capable of manufacturing 7nm chips. If the industry were to continue using DUV for 5nm chip production, fourfold exposure would not be sufficient. It would require 6-8 times of exposure, more mask plates, longer lithography times, and higher material costs, making it unbearable. Therefore, it is better that when 5nm chips were ready, EUV lithography machines are also prepared, thus liberating the industry from the burdensome multiple exposures. As a result, the 7nm chips represents the last generation of processes manufactured using DUV in the industry's current landscape.

快報